The flat cell structure, which is advantageous for finer structures, in a nonvolatile semiconductor storage device such as a NAND flash memory has recently gained attention again.
The flat cell structure has the advantage that half the pitch (half pitch) of bit lines extending in a column direction is not restricted by an inter-electrode insulating layer or a control gate electrode because the inter-electrode insulating layer or the control gate electrode does not get in between floating gate electrodes aligned in a row direction in which a control gate electrode (word line) extends.
However, an opposing area of the floating gate electrode and the control gate electrode is small in the flat cell structure and it is difficult to achieve a sufficiently large coupling ratio. Moreover, if the half pitch is narrowed by the flat cell structure, the so-called inter-cell interference in which memory cells aligned in the row direction interfere with each other in a read or write operation may be caused.
In addition, it is becoming more difficult to achieve a sufficiently large coupling ratio in the flat cell structure with increasingly finer structures of memory cells.